CSCE 932: Fault Tolerance:

Testing and Testable Design

Spring 2009 

University of Nebraska-Lincoln

News

General Information

Instructor:  Sharad C. Seth, Avery Hall, Room 359

Lecture Schedule

Projects

1. Web Links
   

• IEEE 1500 standard (official document)
• ATPG Tools on cse:
  
• HOPE fault simulator: /usr/exportlocal/pkgs/hope-2.0/bin/hope
• ATALANTA ATPG for combinational logic: /usr/exportlocal/pkgs/atalanta/bin/atalanta
• Benchmarks and tools
  
• ISCAS89 scan benchmark circuits
• Harlow, J. E. 2000. Overview of Popular Benchmark Sets. IEEE Des. Test 17, 3 (Jul. 2000), 15-17. DOI= http://dx.doi.org/10.1109/54.867889
• Corno, F.; Reorda, M.S.; Squillero, G., "RT-level ITC'99 benchmarks and first ATPG results," Design & Test of Computers, IEEE , vol.17, no.3, pp.44-53, Jul/Sep 2000. http://0-ieeexplore.ieee.org.library.unl.edu/stamp/stamp.jsp?arnumber=867894&isnumber=18787
• Kapur, R.; Hay, C.; Williams, T.W., "The mutating metric for benchmarking test," Design & Test of Computers, IEEE , vol.17, no.3, pp.18-21, Jul/Sep 2000 URL: http://0-ieeexplore.ieee.org.library.unl.edu/stamp/stamp.jsp?arnumber=867890&isnumber=18787
• Advanced EDA benchmark datasets
  
• ISCAS85 circuits: http://courses.ece.uiuc.edu/ece543/iscas85.html
• ISCAS benchmark in the BLIF format can be downloaded by searching for "iscas benchmarks in BLIF" on the web. The following are two places from which you can download some or all of ISCAS-85 and ISCAS-89 circuits in the BLIF format:
• UCLA course web page.
• U. Wisconsin course web page
  
• Electronic CAD and reliability group web page from Politecnico di Torino
• Benchmark and tools download page (including ISACS'89 and Addendum circuits in EDIF format)
• ITC'99 RTL benchmark circuits
• FPGA CAD Software from the Toronto FPGA Research Group
• EDIF to BLIF converter (available for download from this web page) This converter was written to for EDIF files produced by Altera's MaxPlus2 but may work more generally for EDIF files coming from other sources.
• A  Tutorial of Usage and Programming of SIS (from UCLA CS258G course) .
  
• Courses
• Spring 2007 offering of this course
• ECE 543: Digital System Testing and Design for Testability, Professor Janak Patel, UIUC
• EE386: Robust System Design, Stanford University, Spring Quarter 2007-2008, Professor Subhasish Mitra
• ELEC7250-001 VLSI Testing, Auburn University, Spring 2006, Vishwani Agrawal
• EE382M.1 - VLSI Testing, U. Texas, Austin, Spring 2009, Nur Touba
• Fun Stuff
• Classic paper on reliable design: J. von Neumann, "Probabilistic Logics and the synthesis of reliable organisms from unreliable components," In C. Shannon and J. McCarthy (editors) Automata Studies, pages 43--98, Princeton University Press.
• Gigascale Research Center (GSRC) Berkeley, home page. You may wish to scan the "Recent Papers" link for papers on testing and fault tolerant designs.
• R. Marculescu et al., "Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives," IEEE TCAD, January 2009, pp. 3-21. This keynote paper provides a general description of NoC architectures and applications and enumerates several related problems under the categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation.