3.2. The Modules and Their Functions

The modules in Figure 1 are patterned after the GA operators defined in Goldberg's simple genetic algorithm (SGA) [10]. The HGA modules operate concurrently with each other and together form a coarse-grained pipeline. All modules are written in VHDL and are independent of the operating environment and implementation technology (e.g. Xilinx FPGAs or fabricated chips) except for the memory interface module. The functionality of this module varies according to the physical memory attached to it and the desired interface between the HGA and its user. The basic functionality of the HGA design of Figure 1 is as follows.

1. After all the parameters have been loaded into the shared memory, the memory interface module (MIM) receives a ``Go'' signal from the front end. The MIM acts as the main control unit of the HGA and is the HGA's sole interface to the outside world.
2. The MIM notifies the fitness module (FM), crossover/mutation module (CMM), the pseudorandom number generator (RNG) and the population sequencer (PS) that the HGA is to begin execution. Each of these modules requests its required parameters from the MIM, which fetches them from the appropriate places of the shared memory.
3. The population sequencer starts the pipeline by requesting population members from the MIM and passing them along to the selection module.
4. The task of the selection module (SM) is to receive new members from the PS and judge them until a pair of sufficiently fit members is found based on a random number. At that time it passes the pair to the crossover/mutation module (CMM), resets itself, and restarts the selection process.
5. When the crossover/mutation module receives a selected pair of members from the SM, it decides whether to perform crossover and mutation based on random values sent from the RNG. When done, the new members are sent to the fitness module for evaluation.
6.   The fitness module evaluates the two new members from the CMM and writes the new members to memory through the MIM. The FM also maintains some records concerning the current state of the HGA that are used by the SM to select new members and by the FM to determine when the HGA is finished.
7. The above steps continue until the FM determines that the current HGA run is finished. It then notifies the MIM of completion which in turn shuts down the HGA modules and sends the ``Done'' signal to the front end.

Since the modules of the HGA system were written entirely in VHDL, specific aspects of the design such as I/O bus size, storage facility size, etc. can be specified in terms of parameters which can be easily changed when the need arises. The interesting parameters of the HGA are n, the maximum width in bits of the population members, , the maximum width in bits of the fitness values, , the maximum size of the population, and the maximum number of generations . When module parallelization is involved (Section 3.3), the parameter nsel indicates the number of parallel selection modules. These parameters are specified at VHDL compile time and should not be confused with the HGA run time parameters described in Section 3.1.

Last modified 11 August 1999.